1. Field of the Invention
The method of parasitic extraction of an integrated circuit design for multiple operating conditions disclosed herein is directed to the design and verification of integrated circuits. More specifically, but without limitation thereto, this method is directed to simulating the effects of resistance and capacitance in an integrated circuit design under different operating conditions.
2. Description of Related Art
A step frequently performed in the design of integrated circuits is called parasitic extraction, in which the resistance and capacitance of logic gates and interconnect wires is simulated in a computer model to determine the timing performance of the integrated circuit design.